1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device ensuring stable operation of a memory cell.
2. Description of the Background Art
As an example of a conventional semiconductor device, a semiconductor device provided with a static random access memory (hereinafter referred to as an "SRAM") will be described. An SRAM is a volatile semiconductor device, in which memory cells are placed at crossings of complementary data lines (bit lines) and word lines arranged in a matrix. FIGS. 20A and 20B each show an equivalent circuit of the memory cell. Referring to FIGS. 20A and 20B, each memory cell is composed of a flip-flop circuit F and two access transistors A1 and A2. In flip-flop circuit F, one inverter INV1 having a load element L1 and a driver transistor D1 and the other inverter INV2 having a load element L2 and a driver transistor D2 each have its input terminal and output terminal cross-coupled, thereby forming two storage nodes N1 and N2.
Access transistor A1 has a source region connected to storage node N1, and a drain region connected to one of the complementary bit lines. Similarly, access transistor A2 has a source region connected to storage node N2, and a drain region connected to the other bit line of the complementary bit lines. Driver transistor D1 has a drain region connected (commonly) to the source region of access transistor A1, and a source region connected to a ground line V.sub.EE. The gate electrode of driver transistor D1 is connected to the source region of access transistor A2.
Driver transistor D2 has a drain region connected (commonly) to the source region of access transistor A2, and a source region connected to ground line V.sub.EE. The gate electrode of driver transistor D2 is connected to the source region of access transistor A1. One end of load element L1 is connected to the source region of access transistor A1, and the other end to a power supply line (V.sub.CC line). Similarly, one end of load element L2 is connected to the source region of access transistor A2, and the other end to power supply line (V.sub.CC line).
Gate electrodes of access transistors A1 and A2 are connected to a word line (WL), which controls conduction of access transistors A1 and A2. Storage nodes N1 and N2 have two stable states in which the voltage of one storage node is at a high level and that of the other node is at a low level, or vice versa. This is called a bistable state, and the memory cell will be kept at this bistable state as long as a prescribed power supply voltage is applied thereto.
The operation of the SRAM will now be described. Firstly, when writing data into a specific memory cell, a word line (WL) corresponding to the memory cell conducts access transistors A1 and A2, and forcefully applies a voltage to a pair of the complementary bit lines according to a desired logic value. The potentials of the two storage nodes N1 and N2 of flip-flop circuit F is thus set to the above-described bistable state, with data kept as the potential difference.
For data reading, access transistors A1 and A2 are rendered conductive, the potentials of storage nodes N1 and N2 are transmitted to the bit lines, whereby data are read out.
Next, input/output transfer characteristics indicating the performance characteristics of the above memory cell will be described with reference to drawings. Firstly, FIG. 21 shows the input/output transfer characteristics of a pair of inverters shown in FIG. 20B. In FIG. 21, the ordinate represents the potential of storage node N2, and the abscissa represents the potential of storage node N1. Curved lines C and C1 show correlations of the inputs and outputs of the pair of inverters. In order for the inverters to function as a flip-flop circuit, curved lines C and C1 need to have two intersections, i.e., two stable points S1 and S2. Particularly, a memory cell must be designed to have a sufficiently large area surrounded by curved lines C and C1 to stand up to practical use. Here, the diameter of a circle inscribed in curved lines C and C1 is used as an indicator, as shown in FIG. 21. Specifically, the diameter of this circle is called a static noise margin (SNM).
Next, FIG. 22 shows the input/output transfer characteristics of the memory cell at standby. As access transistors A1 and A2 are not conductive at standby, driver transistors D1 and D2 and load elements L1 and L2 form respective inverters of the memory cell. At this time, load elements L1 and L2 have relatively high impedance, whereby the inverter outputs make steep transitions. Therefore, in this case, the static noise margin is relatively large, enabling the data to be kept stably.
Next, FIG. 23 shows the input/output transfer characteristics of the memory cell at data reading. When reading data out of the memory cell, access transistors A1 and A2 are rendered conductive, so that a column current flows into the storage node at a low level. This results in a condition equivalent to that in which a load with a relatively low impedance is connected in parallel to the load element. Thus, load elements L1 and L2 with high impedance function as if they did not exist. The inverters are therefore regarded as NMOS enhancement type ones with the access transistors serving as a load. The relation of the inputs and outputs of the inverters at this time is expressed as curved lines C and C1, from which it is understood that the inclination of the transition at the inverter outputs is more gentle when it is compared in particular to the inverter outputs at standby. This means that the gain of the inverters at this time is lower than that at standby.
FIG. 24 shows the input/output transfer characteristics of the memory cell at writing data. In the memory cell into which data are to be written, access transistors A1 and A2 are rendered conductive, and the voltage of one of the complementary bit lines is lowered closer to a ground potential (which is called "to pull down") to set the potential of the storage node at a low level.
This will be explained with reference to FIG. 24. Suppose that the memory cell is initially stabilized at S2, i.e., (N1, N2)=("L", "H"). In order to rewrite this data to an opposite data, i.e., (N1, N2)=("H", "L"), the voltage of the bit line connected to access transistor A2 is pulled down. This results in the change of the input/output transfer characteristics of one of the inverters, which have storage node N1 as an input and storage node N2 as an output, from that as expressed by curved line C1 to that as curved line C2. Here, there is only one stable point S1', offering a monostable state, and thus the data is rewritten. When pulling down is stopped to quit data writing, the inverter outputs make transitions to cross point S1 and are stabilized.
In conventional semiconductor devices, several approaches have been taken to attain stable operation of a memory cell in the above-described SRAM. For example, Japanese Patent Laying-Open No. 4-61377 describes an approach to set the threshold voltage of a driver transistor higher than the threshold voltage of an access transistor. That is, the threshold voltage of the access transistor is set even lower.
This will now be described. Especially when reading data, the potential of the storage node at a high level lowers from the power supply voltage at standby to the power supply voltage minus the threshold voltage of an access transistor, causing a static noise margin temporarily lowered considerably at times. Here, if the inverters do not have a sufficient static noise margin, the bistable state will be lost and thus data will be destructed. In order to prevent this from occurring, the threshold voltage of the access transistor is normally kept low to increase the static noise margin of the inverters, and thus stable operation of the memory cell is ensured.
Immediately after a writing operation, the potential of the storage node at a high level rises no more than the power supply voltage minus the threshold voltage of the access transistor, making data vulnerable to external noise and .alpha.-rays. This problem becomes more serious as the voltage is lowered according to the current trend for lower power supply voltages. In view of this, also, lower threshold voltage of the access transistor is advantageous since it ensures a higher power supply voltage, thereby suppressing such data destruction and permitting stable operation of the memory cell.
Herein, a soft error caused by the .alpha.-rays will be described. The incidence of the .alpha.-rays into the storage node at a high level in the memory cell causes electron-hole pairs to generate along the range of the .alpha.-rays. In the depletion layer, electrons out of the electron-hole pairs are attracted to the storage node due to the electric field, which leads to reduction in the potential of the storage node at a high level. The flip-flop current is thus inverted, thereby destructing data. This event is called the .alpha.-ray induced soft error.
In an attempt to increase the static noise margin of an inverter, there has been a method of setting the resistance at the grounded side (connected to the ground line) of the driver transistor as low as possible to stabilize the ground potential. For example, Japanese Patent Laying-Open No. 2-312271 describes a semiconductor device in which a titanium silicide film is formed on the surface of the source region (corresponding to the grounded side) of the driver transistor to lower the resistance at the grounded side. Herein, stabilizing the ground potential means to minimize the potential rise from the 0 V level when a current flows.
As another way of increasing the static noise margin, there has been a method for increasing the ratio of the current drivability of a driver transistor to the current drivability of an access transistor (i.e. the .beta. ratio). The increase of the .beta. ratio leads to the increase of the inverter gain, so that the operation of the memory cell becomes stable. For the purpose of increasing the .beta. ratio, the gate width of the driver transistor is normally set to be greater than the gate width of the access transistor. Setting the gate width greater, however, hinders reduction in the space occupied by a memory cell region, and therefore a higher degree of integration of a semiconductor device cannot be attained easily.
As such, another method of increasing the .beta. ratio by providing the driver transistor with a greater current drivability has been currently adapted. As an example, one of such methods increases the current drivability of the driver transistor by setting higher the impurity concentration of the source-drain regions of the driver transistor to reduce the parasitic resistance.
As a still another method of increasing the static noise margin, there has been a method of setting the threshold voltage of the driver transistor still higher. At standby, access transistors are not conductive, and therefore the inverters of a memory cell are formed by respective driver transistors D1 and D2 and load elements L1 and L2. At this time, in the inverter having a storage node at a high level, if the sub-threshold leakage current of the driver transistor is the same as or larger than the current flowing through the load element, a current will flow from the storage node through the driver transistor to the grounded side, and the high level cannot be held. Therefore, the threshold voltage of the driver transistor is, desirably, to be set higher so as to reduce the sub-threshold leakage current.
As described above, in order to increase the static noise margin of the inverters in a semiconductor device, it is preferable that the threshold voltage of an access transistor is set lower, the threshold voltage of a driver transistor is set higher, and the threshold voltage of the driver transistor is set higher than the threshold voltage of the access transistor. A threshold voltage of a transistor is controlled by introduction of a prescribed amount of impurities into a semiconductor substrate. Therefore, in order to attain the above-described relation of the threshold voltages, it is necessary to set the impurity concentration at a region in a semiconductor substrate directly below the gate electrode of the driver transistor higher than that of the access transistor.
However, in order to form regions with different impurity concentrations directly below the respective gate electrodes of the access transistor and the driver transistor on a single semiconductor substrate, a mask must be provided when infusing impurities into such regions beneath the respective gate electrodes. A photoresist pattern is used as such an implant mask, and the need for a new mask possibly increases manufacturing cost.
Further, miniaturization of semiconductor devices has caused innegligible misalignment in terms of patterning the above-described photoresist. This results in fluctuation of threshold voltage of transistors, e.g., the rise of the threshold voltage of an access transistor, making it difficult to attain stable operation of a semiconductor device.
Moreover, suppose that the above-described method for increasing the current drivability of a driver transistor is taken in an attempt to increase the static noise margin of an inverter. When, for example, the impurity concentrations of both the source and drain regions of the driver transistor are set higher than the impurity concentration of the drain region of the access transistor, the effective gate length of the driver transistor can become too short. This may cause punch through in the driver transistor, and thus again, it becomes difficult to attain stable operation of the semiconductor device as desired.